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tc55vzm216ajji/afti08,10,12 2003-01-17 1/11 ? single power supply voltage of 3.3 v 0.3 v ? fully static operation ? operating temperature range of ? 40 to 85c ? all inputs and outputs are lvttl compatible ? output buffer control using oe ? data byte control using lb (i/o1 to i/o8) and ub (i/o9 to i/o16) ? package: soj44-p-400-1.27 (ajji) (weight: 1.64 g typ) tsop ii44-p-400-0.80 (afti) (weight: 0.45 g typ) toshiba mos digital integrated circuit silicon gate cmos 262,144-word by 16-bit cmos static ram description the tc55vzm216ajji/afti is a 4,194,304-bit high-speed static random access memory (sram) organized as 262,144 words by 16 bits. fabricated using cmos technology and advanced circuit techniques to provide high speed, it operates from a single 3.3 v power supply. chip enable ( ce ) can be used to place the device in a low-power mode, and output enable ( oe ) provides fast memory access. data byte control signals ( lb , ub ) provide lower and upper byte access. this device is well suited to cache memory applications where high-speed access and high-speed storage are required. all inputs and outputs are directly lvttl compatible. the tc55vzm216ajji/afti is available in plastic 44-pin soj and tsop with 400mil width for high density surface assembly. the tc55vzm216ajji/afti guarantees ? 40 to 85c operating temperature so it is suitable for use in wide operating temperature system. features ? fast access time (the following are maximum values) tc55vzm216ajji/afti08:8 ns tc55vzm216ajji/afti10:10 ns tc55vzm216ajji/afti12:12 ns ? low-power dissipation (i ddo2 ) (the following are maximum values) cycle time 8 10 12 ns operation (max) 150 140 130 ma standby:10 ma (both devices) pin assignment (top view) pin names 44 pin soj 44 pin tsop a0 to a17 address inputs i/o1 to i/o16 data inputs/outputs ce chip enable input we write enable input oe output enable input lb , ub data byte control inputs v dd power ( + 3.3 v) gnd ground nu not usable (input) a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 i/o4 v dd gnd i/o5 i/o6 i/o7 i/o8 a15 a14 a13 a12 a16 a5 a6 a7 i/o16 i/o15 i/o14 i/o13 gnd v dd i/o12 i/o11 i/o10 i/o9 nu a8 a9 a10 a11 a17 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 ce oe ub lb we 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 i/o4 v dd gnd i/o5 i/o6 i/o7 i/o8 a15 a14 a13 a12 a16 a5 a6 a7 i/o16 i/o15 i/o14 i/o13 gnd v dd i/o12 i/o11 i/o10 i/o9 nu a8 a9 a10 a11 a17 oe ub lb ce we (tc55vzm216ajji) (tc55vzm216afti)
tc55vzm216ajji/afti08,10,12 2003-01-17 2/11 block diagram maximum ratings symbol rating value unit v dd power supply voltage ? 0.5 to 4.6 v v in input terminal voltage ? 0.5 * to 4.6 v v i/o input/output terminal voltage ? 0.5 * to v dd + 0.5 ** v p d power dissipation 1.4 w t solder soldering temperature (10s) 260 c t stg storage temperature ? 65 to 150 c t opr operating temperature ? 40 to 100 c * : ? 1.5 v with a pulse width of 20% of t rc min (4 ns max) ** : v dd + 1.5 v with a pulse width of 20% of t rc min (4 ns max) i/o1 ce v dd gnd i/o8 we ce ce i/o9 oe ub lb ce a2 a3 a6 a7 a10 a11 a12 a0 a1 a4 a5 a8 a9 a13 a14 a15 a17 a16 clock generator column address buffer column decoder sense amp memory cell array 1,024 256 16 (4,194,304) i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 i/o16 data output buffer data input buffer data input buffer data output buffer row address buffer row decoder
tc55vzm216ajji/afti08,10,12 2003-01-17 3/11 dc recommended operating conditions (ta = = = = ? ? ? ? 40 to 85c) symbol parameter min typ max unit v dd power supply voltage 3.0 3.3 3.6 v v ih input high voltage 2.0 ? v dd + 0.3 ** v v il input low voltage ? 0.3 * ? 0.8 v * : ? 1.0 v with a pulse width of 20% of t rc min (4 ns max) ** : v dd + 1.0 v with a pulse width of 20% of t rc min (4 ns max) dc characteristics (ta = = = = ? ? ? ? 40 to 85c, v dd = = = = 3.3 v 0.3 v) symbol parameter test condition min typ max unit i il input leakage current (except nu pin) v in = 0 to v dd ? 1 ? 1 a i lo output leakage current ce = v ih or we = v il or oe = v ih , v out = 0 to v dd ? 1 ? 1 a i i (nu) input leakage current (nu pin) v in = 0 v ? 1 ? 1 a i oh = ? 2 ma 2.4 ? ? v oh output high voltage i oh = ? 100 a v dd ? 0.2 ? ? i ol = 2 ma ? ? 0.4 v ol output low voltage i ol = 100 a ? ? 0.2 v t cycle = 8 ns ? ? 180 t cycle = 10 ns ? ? 170 i ddo1 ce = v il , i out = 0 ma, oe = v ih , other input = v ih /v il t cycle = 12 ns ? ? 160 t cycle = 8 ns ? ? 150 t cycle = 10 ns ? ? 140 i ddo2 operating current ce = 0.2 v, i out = 0 ma, oe = v dd ? 0.2 v, other input = v dd ? 0.2 v/0.2 v t cycle = 12 ns ? ? 130 ma i dds1 ce = v ih , other input = v ih or v il ? ? 65 i dds2 standby current ce = v dd ? 0.2 v, other input = v dd ? 0.2 v or 0.2 v ? ? 10 ma capacitance (ta = = = = 25c, f = = = = 1 .0 mhz) symbol parameter test condition max unit c in input capacitance v in = gnd 6 pf c i/o input/output capacitance v i/o = gnd 8 pf note: this parameter is periodically sampled and is not 100% tested.
tc55vzm216ajji/afti08,10,12 2003-01-17 4/11 operating mode mode ce oe we lb ub i/o1 to i/o8 i/o9 to i/o16 power l l output output i ddo h l high impedance output i ddo read l l h l h output high impedance i ddo l l input input i ddo h l high impedance input i ddo write l * l l h input high impedance i ddo l h h * * outputs disable l * * h h high impedance high impedance i ddo standby h * * * * high impedance high impedance i dds * : don?t care note: the nu pin must be left unconnected or tied to gnd. you must not apply a voltage of more than 0.8 v to the nu.
tc55vzm216ajji/afti08,10,12 2003-01-17 5/11 ac characteristics (ta = = = = ? ? ? ? 40 to 85c (see note 1) , v dd = = = = 3.3 v 0.3 v) read cycle tc55vzm216ajji/afti 08 10 12 symbol parameter min max min max min max unit t rc read cycle time 8 ? 10 ? 12 ? t acc address access time ? 8 ? 10 ? 12 t co chip enable access time ? 8 ? 10 ? 12 t oe output enable access time ? 4 ? 5 ? 6 t ba upper byte, lower byte access time ? 4 ? 5 ? 6 t oh output data hold time from address change 3 ? 3 ? 3 ? t coe output enable time from chip enable 3 ? 3 ? 3 ? t oee output enable time from output enable 0 ? 0 ? 0 ? t be output enable time from upper byte, lower byte 0 ? 0 ? 0 ? t cod output disable time from chip enable ? 4 ? 5 ? 6 t odo output disable time from output enable ? 4 ? 5 ? 6 t bd output disable time from upper byte, lower byte ? 4 ? 5 ? 6 ns write cycle tc55vzm216ajji/afti 08 10 12 symbol parameter min max min max min max unit t wc write cycle time 8 ? 10 ? 12 ? t wp write pulse width 6 ? 7 ? 8 ? t cw chip enable to end of write 6 ? 7 ? 8 ? t bw upper byte, lower byte enable to end of write 6 ? 7 ? 8 ? t aw address valid to end of write 6 ? 7 ? 8 ? t as address setup time 0 ? 0 ? 0 ? t wr write recovery time 0 ? 0 ? 0 ? t ds data setup time 4 ? 5 ? 6 ? t dh data hold time 0 ? 0 ? 0 ? t oew output enable time from write enable 3 ? 3 ? 3 ? t odw output disable time from write enable ? 4 ? 5 ? 6 ns ac test conditions fig.1 parameter test condition input pulse level 3.0 v/ 0.0 v input pulse rise and fall time 2 ns input timing measurement reference level 1.5 v output timing measurement reference level 1.5 v output load fig.1 i/o pin c l = 30 pf z 0 = 50 ? r l = 50 ? v l = 1.5 v i/o pin c l = 5 pf 870 ? (for t coe , t oee , t be , t cod , t bd , t odo , t oew and t odw ) 3.3 v 1200 ?
tc55vzm216ajji/afti08,10,12 2003-01-17 6/11 timing diagrams read cycle (see note 2) write cycle 1 ( controlled) (see note 5) we ub , lb address oe d out t rc t acc t oh valid data out t oe hi-z hi-z t co ce t ba t oee (see note 6) t coe (see note 6) t odo (see note 6) indeterminate indeterminate t cod (see note 6) t bd (see note 6) t be (see note 6) address we ub , lb d out t aw t as t bw t wr valid data in d in t wp t ds t dh hi-z t cw ce t wc t odw (see note 6) t oew (see note 6) (see note 3) indeterminate (see note 4) indeterminate
tc55vzm216ajji/afti08,10,12 2003-01-17 7/11 write cycle 2 ( controlled) (see note 5) write cycle 2 ( , controlled) (see note 5) ub lb address t wc t wp t as t bw t wr valid data in t ds t dh hi-z hi-z t aw t cw we ub , lb d out d in ce t odw (see note 6) indeterminate t be (see note 6) (see note 6) t coe ce address t wc t wp t as t cw t wr valid data in t ds t dh hi-z hi-z t aw t bw we ub , lb d out d in ce t odw (see note 6) indeterminate t coe (see note 6) (see note 6) t be
tc55vzm216ajji/afti08,10,12 2003-01-17 8/11 note: (1) operating temperature (ta) is guaranteed for transverse air flow exceeding 400 linear feet per minute. (2) we remains high for the read cycle. (3) if ce goes low coincident with or after we goes low, the outputs will remain at high impedance. (4) if ce goes high coincident with or before we goes high, the outputs will remain at high impedance. (5) if oe is high during the write cycle, the outputs will remain at high impedance. (6) the parameters specified below are measured using the load shown in fig.1. (a) t coe , t oee , t be , t oew kkkkkkkkkkkk output enable time (b) t cod , t odo , t bd , t odw kkkkkkkkkkkk output disable time we d out (a) valid data out 0.2 v 0.2 v (b) 0.2 v 0.2 v indeterminate hi-z hi-z ce , oe ub , lb indeterminate
tc55vzm216ajji/afti08,10,12 2003-01-17 9/11 package dimensions soj44-p-400-1.27 weight: 1.64 g (typ)
tc55vzm216ajji/afti08,10,12 2003-01-17 10/11 package dimensions weight: 0.45 g (typ)
tc55vzm216ajji/afti08,10,12 2003-01-17 11/11 ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ? handling guide for semiconductor devices, ? or ? toshiba semiconductor reliability handbook ? etc.. ? the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ( ? unintended usage ? ). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer ? s own risk. ? the products described in this document are subject to the foreign exchange and foreign trade laws. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. ? the information contained herein is subject to change without notice. 000707eba restrictions on product use

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